The present invention relates to clock signal generators suitable for use in an integrated circuit memory device. More particularly, the present invention relates to an internal clock signal generator for synchronizing an internal clock with an external clock signal.
Integrated circuit devices such as an integrated circuit memory or central processing units, which operate in synchronization with an external clock signal, typically generate an internal clock signal using a clock buffer and a clock driver. As a result, the internal clock signal may be delayed compared to the external clock signal. Such a delay may cause deterioration in the performance of the device during high frequency operation. In particular, at high frequencies of operation, the access time tac (i.e., the time required for outputting data after an external clock signal is input) may become longer than the time required for generating an internal clock signal from the received external clock signal. Deterioration of the performance of a semiconductor device at higher frequencies may be reduced by synchronizing the internal clock signal with the external clock signal. Conventionally, this synchronization may be accomplished with a delay locked loop (DLL) or a phase locked loop (PLL) which are used as the internal clock signal generator.
FIG. 1 is a schematic diagram of a conventional DLL. As seen in FIG. 1, the DLL includes a phase detector 1, a low pass filter (LFF) 2, and a voltage control delay line 3. The phase detector 1 compares the phases of an external clock signal Ext.CLK and an internal clock signal Int.CLK and detects the difference between the phases. The LPF 2 is connected to the output of the phase detector 1 and generates a control voltage vcont for controlling the delay time of the voltage control delay line 3. The voltage control delay line 3 typically includes a plurality of inverters which are serially connected and outputs the internal clock signal Int.CLK by delaying the external clock signal by a predetermined time specified by the voltage control input. Unfortunately, however, synchronizing the internal clock signal with the external clock signal may take hundreds of cycles of the external clock signal. Furthermore, the DLL circuit may require several tens of milliamps of current during operation. Therefore, it may be difficult to utilize the DLL in an integrated circuit device.
FIG. 2 is a schematic diagram of a conventional PLL. As seen in FIG. 2, the PLL includes a phase-frequency detector 11, a LPF 12, and a voltage control delay line 13. The phase-frequency detector 11 compares the phases and frequencies of the external clock signal Ext.CLK and the internal clock signal Int.CLK, and detects the differences in phases and frequencies. The LPF 12 is connected to the output of the phase detector 11 and generates a control voltage vcont for controlling the delay time of the voltage control delay line 13. The voltage control delay line 13 outputs the internal clock signal Int.CLK in response to the control voltage vcont and the internal clock signal Int.CLK which is fed back to the input of the voltage control delay line 13. Thus, the voltage control delay line 13 acts as a ring oscillator.
The PLL of FIG. 2, however, may have the same problems as the DLL of FIG. 1. Recently, the PLL and the DLL have been coupled together to utilize the quick locking time of the PLL and the wide locking range of the DLL. However, this combination may not solve all of the problems with the DLL and the PLL.
As a result of the shortcomings of the PLL and the DLL, a synchronized delay circuit has been suggested which uses simple delay means to match the phase of the internal clock signal with the phase of the external clock signal. This phase matching may be accomplished by making the delay time of the internal clock signal an integer multiple of the period of the external clock signal. In such a system, a synchronous delay line (SDL), a synchronous mirror delay (SMD), and a hierarchical phase lock delay (HPLD) may be utilized as the synchronized delay circuit.
FIG. 3 is a schematic diagram of a conventional synchronous delay circuit. As seen in FIG. 3, the synchronous delay line includes a clock buffer 21, a dummy clock delay 22, a first clock delay portion 23, a comparing portion 24, a second clock delay portion 25, and a clock driver 26. In the circuit of FIG. 3, the clock buffer 21 receives an external clock signal Ext.CLK and outputs a first clock signal CLK1 in which the external clock signal is delayed by a first delay time d1. As is further seen in FIG. 3, tCK represents the period of the external clock signal. The dummy clock delay 22 controls the phase difference between the external clock signal and internal clock signal Int.CLK such that the phase difference is an integer multiple of the period tCK. The dummy clock delay 22 delays the first clock signal CLK1 by the sum of the first delay time d1 and a second delay time d2 to provide a second clock signal CLK2.
The first clock delay portion 23 includes first unit delays 27 which are serially connected and which output a third clock signal CLK3. The output CLK3 is a delayed version of the second clock signal CLK2 and may be delayed by different times. The comparing portion 24 includes a plurality of comparators 28 which compare the first clock signal CLK1 with the third clock signal CLK3 delayed by the period tCK from the first clock signal CLK1. Thus, a fourth clock signal is delayed by the difference between the period tCK and the sum of the first and second delay times d1 and d2 compared with the second clock signal CLK2.
The second clock delay portion 25 includes second unit delays 29 which are connected in series and output a fifth clock signal CLK5 by delaying the first clock signal CLK1 by the difference between the period tCK and the sum of the first and second delay times d1 and d2. The clock driver 26 outputs the internal clock signal Int.CLK delayed by the second delay time d2 by receiving the fifth clock signal CLK5. FIG. 4 is a timing diagram illustrating the operational state of the synchronous delay line of FIG. 3. As seen in FIG. 4, the first clock signal CLK1 is delayed by a first time d1 when compared with the external clock signal Ext.CLK. The second clock signal CLK2 is delayed by the sum of the first delay time d1 and a second delay time d2 compared with the first clock signal CLK1. The third clock signal CLK3 is the second clock signal CLK2 delayed by an integer multiple of the delay time of the first unit delay 27. The fourth clock signal CLK4 is one of the third clock signal CLK3 which was delayed by an integer multiple of the period tCK of the external clock Ext.CLK. In the embodiment illustrated in FIG. 3, the fourth clock signal CLK4 corresponds to the clock signal CLK1 delayed by one period of the external clock signal.
The fifth clock signal CLK5 corresponds to the fourth clock signal CLK4 delayed by the difference tCK minus (d1+d2) between the period tCK of the external clock signal Ext.CLK and the sum of the first delay time d1 and the second delay time d2. The Internal clock signal Int.CLK then corresponds to the fifth clock signal CLK5 delayed by the second delay time d2. Thus, the internal clock signal Int.CLK is delayed from the external clock signal Ext.CLK by twice the period tCK of the external clock signal. Thus, the internal clock signal Int.CLK is synchronized with the external clock signal Ext.CLK.
The conventional SDL circuit described above is an open loop circuit unlike the PLL and DLL circuits which are closed loop circuits. Thus, the locking time of the SDL circuit is an integer multiple of the period tCK of the external clock signal. Accordingly, the locking time of the SDL circuit may be shorter than the locking time of the PLL and DLL circuits. However, the degree of locking accuracy of the SDL circuit may be lower than the PLL or DLL circuits because the SDL circuits may have a narrow margin of its locking range.
In view of the above discussion, it is an object of the present invention to provide for the synchronization of an internal clock to an external clock with less delay in locking to the external clock signal than may be experienced in using a phase locked loop or a delay locked loop.
Another object of the present invention is to provide an internal clock which can be more closely synchronized to an external clock than is provided in a synchronized delay circuit.
These and other objects of the present invention are provided by an internal clock signal generator which utilizes a synchronized delay circuit to provide a coarsely synchronized clock signal which is then more finely synchronized to the external clock by either a delay locked loop or a phase locked loop. By first synchronizing the signal to the external clock with a synchronized delay circuit the coarse clock signal may be rapidly generated. By utilizing the coarse clock signal with either the delay locked loop or the phase locked loop, these loops may more quickly lock on the external clock signal to provide the finely synchronized signal. Thus, the advantages of both the synchronized delay line and the delay or phase locked loops may be obtained through use of the present invention.
In a particular embodiment of the present invention, an internal clock signal generator is provided which includes a synchronized delay circuit which receives an external clock signal and outputs a clock signal which is coarsely synchronized with the external clock signal. A delay locked loop (DLL) receives the coarsely synchronized clock signal and generates an internal clock signal which is more finely synchronized with the external clock signal.
In an alternative embodiment, a phase locked loop (DLL) receives a coarsely synchronized clock signal and generates an internal clock signal which is more finely synchronized with the external clock signal.
In particular embodiments of the present invention, the synchronized delay circuit is one of synchronous a delay line (SDL), a synchronous mirror delay (SMD) and a hierarchical phase locking delay (HPLD). Accordingly, the synchronized delay circuit may include a plurality of serially connected unit delays which provide a corresponding plurality of delayed clock signals. A controller selects one of the plurality of clock signals which is coarsely synchronized with the external clock signal and generates a flag signal for enabling the DLL or the PLL. The DLL or PLL is enabled by the flag signal and generates the internal clock signal which corresponds to the external clock signal delayed by an integer multiple of the period of the external clock signal.
The synchronized delay circuit may also include a clock buffer which receives the external clock signal and outputs a delayed first clock signal corresponding to the external clock signal delayed by a first delay time. A first dummy clock delay receives the delayed first clock signal and outputs a second delayed clock signal corresponding to the first delayed clock signal delayed by a second delay time. A first variable clock delay circuit receives the second delayed clock and outputs a plurality of third delayed clock signals corresponding to the second delayed clock delayed by integer multiples of a unit delay time. A plurality of comparators receive the third delayed clock signals and the first delayed clock signal and compare the phases of each third clock signal and the first clock signal to generate first control signals and the flag signal.
In a particular embodiment, the DLL includes a second variable clock delay circuit which receives the first delayed clock and which generates a plurality of fourth delayed clock signals corresponding to the first delayed clock delayed by integer multiples of a second unit delay time. The second variable clock delay further includes switching means responsive to the first control signals for selectively outputting one of the plurality of fourth delayed clock signals where the duration of the second unit delay time is controlled by a second control signal. A clock driver receives the selected fourth clock signals and outputs the fourth clock signal delayed by a predetermined time so as to provide an internal clock signal. A second dummy clock delay receives the internal clock signal and outputs the fourth clock signal delayed by a fourth delay time so as to provide a fifth delayed clock signal. A phase detector receives the fifth delayed clock signal and the first delayed clock signal and detects the phase difference therebetween. A low pass filter (LPF) connected to the output of the phase detector outputs the second control voltage so as to control the second unit delay time.
In further embodiments of the present invention, the second delay time is the sum of the delay time of the clock buffer and the delay time of the clock driver. The second unit delay time may also vary between the unit delay time and twice the unit delay time based on the second control voltage. The fourth delay time may also be equal to the delay time of the clock buffer. The second variable clock delay circuit may also be a voltage-controlled delay line in which the second unit delays are controlled by the second control voltage and the flag signal. The second variable clock delay circuit may also output one of the plurality of third clock signals whose phase coincides with that of the first clock signal.
In yet another embodiment of the present invention, each comparator includes a first latch which latches one of the plurality of third clock signals when the first clock signal is in a one logic state. A second latch latches the output of the first latch when the first clock signal transitions to a zero logic state. The output of the second latch then generates a first control signal which controls the switching means corresponding to the comparator. The flag signal may also be generated by a combination of first control signals generated by the comparators. A plurality of comparators receive the third delayed clock signals and the first delayed clock signal and compare the phases of each third clock signal and the first clock signal to generate first control signals and the flag signal.
In a particular embodiment of the present invention, the PLL includes a second variable clock delay circuit which receives the first delayed clock and which generates a plurality of fourth delayed clock signals corresponding to the first delayed clock delayed by integer multiples of a second unit delay time. The second variable clock delay further includes switching means responsive to the first control signals for selectively outputting one of the plurality of fourth delayed clock signals and wherein the duration of the second unit delay time is controlled by a second control signal. A clock driver receives the selected fourth clock signals and outputs the fourth clock signal delayed by a predetermined time so as to provide an internal clock signal. A second dummy clock delay receives the internal clock signal and outputs the fourth clock signal delayed by a fourth delay time so as to provide a fifth delayed clock signal. An inverter for inverting the fifth delayed clock signal output from the second dummy clock delay provides an inverted fifth delayed clock signal. A phase detector receives the inverted fifth delayed clock signal and the first delayed clock signal and detects the phase difference therebetween. A low pass filter (LPF) connected to the output of the phase detector outputs the second control voltage so as to control the second unit delay time.
In another embodiment, the second variable clock delay circuit is controlled by the second control voltage and forms an oscillator together with the clock buffer, the second dummy clock delay and the inverter.